The memory cells of dynamic random access memories are comprised of two main components: a field-effect transistor and a capacitor. In DRAM cells utilizing a conventional planar capacitor (such as the one depicted in FIG. 1), far more chip surface area is dedicated to planar capacitor 11 than to field-effect transistor (FET) 12. The gate 13 of FET 12 and the word line 14 are formed from an etched polycrystalline silicon-1 layer. Bit line 15 connects with access-node junction 16. Capacitor 11 has a lower plate formed from the n+ silicon substrate extension 17 of storage-node junction 18 of FET 12. Upper capacitor plate (or field plate) 19 is formed from a layer of conductively-doped polycrystalline silicon. Substrate extension 17 is electrically insulated from upper plate 19 by a dielectric layer 20. Planar capacitors have generally proven adequate for use in DRAM chips up to the one-megabit level. However, planar capacitors constructed with conventional dielectric materials appear to be unusable beyond the one-megabit DRAM level. As component density in memory chips has increased, the shrinkage of cell capacitor size has resulted in a number of problems. Firstly, the alpha-particle component of normal background radiation will generate hole-electron pairs in the n+ silicon substrate plate of a cell capacitor. This phenomena will cause the charge within the affected cell capacitor to rapidly dissipate, resulting in a "soft" error. Secondly, as cell capacitance is reduced, the sense-amp differential signal is reduced. This aggravates noise sensitivity and makes it more difficult to design a sense-amp having appropriate signal selectivity. Thirdly, as cell capacitance is decreased, the cell refresh time must generally be shortened, thus requiring more frequent interruptions for refresh overhead. The difficult goal of a DRAM designer is therefore to increase or, at least, maintain cell capacitance as cell size shrinks, without resorting to processes that reduce product yield or that markedly increase the number of masking and deposition steps in the production process.
Several methods for providing adequate cell capacitance in the face of shrinking cell size are either in use or under investigation. Basically, the efforts fall into two categories. Efforts within the first category are aimed at creating complex three-dimensional capacitors; those within the second are aimed at improving the dielectric of the planar capacitor.
The three-dimensional technique currently receiving the most attention involves the creation of "trench" capacitors in the cell substrate. FIG. 2 depicts a DRAM cell having a typical trench capacitor 21. Similar in concept to planar capacitor 11 of FIG. 1, the trench is employed to provide greater plate area, and hence, greater capacitance. The lower plate 22 may be formed from the n+ doped silicon substrate or it may be formed from a polysilicon layer which lines a trench cut in the n+ doped silicon substrate. The upper plate 23 is formed from a layer of conductively-doped polycrystalline silicon. Lower plate 22 and upper plate 23 are electrically insulated with a dielectric layer 24. DRAM chips employing trench capacitors have been built by a number of European, Japanese and U.S. companies, including IBM Corporation, Texas Instruments Inc., Nippon Electric Company, Toshiba, Matsuchita and Mitsubishi Electric Corporation. There are several problems inherent in the trench design, not the least of which is trench-to-trench capacitive charge leakage which is the result of a parasitic transistor effect between trenches. Another problem is the difficulty of completely cleaning the capacitor trenches during the fabrication process; failure to completely clean a trench will generally result in a defective cell.
Another three-dimensional technique, which is being used by Mitsubishi Electric Company, Hitachi, and Fujitsu Ltd., is the stacking of capacitor plates between dielectric layers on the DRAM cell surface. FIG. 3 is a graphic representation of a typical DRAM cell having a stacked capacitor 31. The lower plate 32 is formed from an n-type polycrystalline silicon layer which is in contact with the silicon substrate 33 in the region of the FET storage-node junction, while the upper plate 34 is formed from a conductively-doped polycrystalline silicon layer. The two layers are separated by a dielectric layer 35. Lower plate 32 and upper plate 34 are both stacked on top of FET 12 and word line 36, resulting in a high-profile cell which requires more stringent process control for the connection of bit line 37 to access-node junction 38.
Alternatively, other schemes involve the use of ferroelectric materials for DRAM cell capacitor dielectrics. Since ferroelectric materials have a dielectric constant more than 100 times that of silicon oxides, the use of such materials has the potential for allowing the size of the DRAM-cell capacitor to be shrunk to one of the smaller cell elements without resorting to three-dimensional structures. Critics of ferroelectric materials point out that such materials suffer from a "wearout" mechanism. In addition, they warn that there are many chemical incompatibilities with the other materials used in integrated circuit fabrication and that the layering of ferroelectric films within integrated circuit structures has not yet been done successfully.